For more information visit the System Chip Design Laboratory Website
The System Chip Design Laboratory (SCDL, formerly the SCDC) was initiated in 1999 by The Western Design Center, Inc. (WDC), an innovator in the development of microprocessor and peripheral intellectual property (IP). SCDL is a research facility of Department of Electrical and Computer Engineering in the College of Engineering. SCDL is a direct descendant of the Advanced Processor Systems Laboratory (APSL) which was established in 1987 and utilized the Intel iRMX III real-time, multitasking operating system executing on the Intel Multibus II multiprocessor computer system and integrated the AT&T Microelectronics DSP32C digital signal processing microprocessors.
The mission of the SCDL is to forge a new paradigm for the rapid design of complex digital systems, digital signal and image processing, digital communications, and advanced processor systems in programmable gate arrays (PGA) reconfigurable system-on-chip (SOC) architectures utilizing behavioral analysis and synthesis and industry-standard digital design and embedded system computer aided (CAD) software tools.
Facilities for behavioral and hardware synthesis include the complete integrated synthesis environment (ISE) design suite from Xilinx executing on Windows XP/Vista and Linux PC engineering workstations. The SCDL is located in the College of Engineering Building on the Main Campus of Temple University, Philadelphia.
The SCDL is an Educational facility with a mandate to meld the traditional threads of digital logic design to the SOC paradigm of the PGA architecture in both undergraduate and graduate engineering education. Faculty and student resources are provided for this mission and for curriculum development.
The SCDL is a Research facility that pursues innovative investigations and solicits tasks from industry with strict adherence to an Non-Disclosure Agreement (NDA), documentation, and timely completion of projects. SCDL trains talented undergraduate and graduate students in the SOC design methodology that utilizes hard processor intellectual property (IP) cores, configurable SOC and soft core architectures on PGAs, on-chip busing arbitration architectures, and heterogeneous multiple processor real-time operating systems (RTOS).
An emphasis of the SCDL is the utilization of Xilinx field programmable gate arrays (FPGA) and ISE tools in undergraduate and graduate courses as part of the Xilinx University Program. The SCDL is responsible for the undergraduate courses and laboratories in digital logic, microprocessor systems, embedded system design and advanced processors.
Contemporary graduate research in Computational Communications is focusing on parallel processing in FPGAs and advanced CAD tools and techniques.