Monday, Wednesday and Fridays 12:00PM - 1:00PM
Shianling Wu is the Director of the Department of Electrical and Computer Engineering's Professional Science Masters-Computer and Systems Security (PSM-C&S Security) Program, with concentration on the physical and hardware aspects of the Cyber Security paradigm. Her technical expertise is in Electronics Design Automation (EDA) tools for semiconductor Integrated Circuit (IC) Design-for-Test, specializing in Built-in Self-Test for device logic and memories. Her industry experience includes leading and managing R&D teams to build over 15 EDA tools for IC testability and supporting world-wide EDA users. She is also a certified project manager experienced in managing multinational projects. She has 13 patents, 6 journal papers, 21 publications, and 1 book chapter. She is a Senior IEEE member, the recipient of IEEE Meritorious Service Award and a Best Panel Session Award from IEEE International Test Conference (ITC). Representing her companies, she was a member of SEMATECH on Test, ITC Program Committee, and IEEE1500 Standards Committee, a contributor to the Asian Test Symposium, and an industry liaison to the North Atlantic Test Workshop.
- M.S., Computer Science – Columbia University, School of Engineering and Applied Science
- B.S., Computer Science – City College of New York, School of Engineering
- Cyber Security: Technology, Application and Policy, Certificate of Completion – MIT Professional Education
- Project Management Professional (PMP) Certification – The Project Management Institute®
- VP of Engineering, SynTest Technologies, Inc., Sunnyvale, CA
- Technical Manager, Bell Laboratories, Hopewell, NJ & Allentown, PA
 S. Wu, et al.,“Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,” ACM Transactions on Design Automation of Electronic Systems, Vol. 17, Issue 4, Article No. 48, October 2012.
 S. Wu, et al., “Physical-Design-Friendly Hierarchical Logic Built-In Self-Test – A Case Study,” Proc. IEEE 2012 International Symposium on Quality Electronic Design (ISQED-2012), Santa Clara, CA, March 2012.
 S. Wu, et al., “Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 3, pp. 456-463, March 2011.
 S. Wu, et al.,“Architectures for Testing 3D Chips Using Time-Division Demultiplexing/ Multiplexing,” IEEE 3D-TEST Workshop, Anaheim, CA, September 2011.
 S. Wu, et al., “Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, pp. 299-312, February 2010.
 L.-T. Wang, N. A. Touba, M. S. Hsiao, Z. Jiang, S. Wu, “Method and apparatus for testing 3D integrated circuits,” United States Patent No. 8,522,096, August 27, 2013.
 L.-T. Wang, S. Wu, Z. Jiang, J. Liu, H.-J. Chao, L. Yu, F. Zhao, F. Li, and J. Yan, “Multiple-Capture DFT System to Reduce Peak Capture Power During Self-Test or Scan-Test,” United States Patent No. 8,091,002, January 3, 2012.
 L.-T. Wang, N. A. Touba, Z. Jiang, S. Wu, and R. Apte, “Robust Scan Synthesis for Protecting Soft Errors,” United States Patent Application No. 12,508,977, allowed December 20, 2011.
 N. A. Touba, L.-T. Wang, Z. Jiang, S. Wu, and J. Yan, “Method and Apparatus for Low-Pin Count Scan Compression,” United States Patent No. 7,996,741, August 9, 2011.